The present invention relates to data storage systems, and more particularly, this invention relates to symbol timing recovery on magnetic media having parallel tracks that are written, and read, simultaneously.
In magnetic storage systems, magnetic transducers read data from and write data onto magnetic recording media. Data is written on the magnetic recording media by moving a magnetic recording transducer to a position on the media where the data is to be stored. The magnetic recording transducer then generates a magnetic field, which encodes the data into the magnetic media. Data is read from the media by similarly positioning the magnetic read transducer and then sensing the magnetic field of the magnetic media. Read and write operations may be independently synchronized with the movement of the media to ensure that the data can be read from and written to the desired location on the media.
In some instances of tape recording, multiple (e.g., 4, 8, 16, or more) parallel data tracks are written simultaneously onto magnetic media by means of a write module comprising an array of write elements/transducers. During a read operation, a read module comprising an array of magneto-resistive read elements/transducers simultaneously produces readback signals of the parallel written data tracks, from which parallel read channel circuitry detects/decodes the written data.
Symbol timing recovery (STR) during readback represents one of the most critical operations in read channels for data storage systems. Symbol timing recovery attempts to recover the optimum sampling time of an analog or digital waveform. A STR scheme typically includes, for each read channel, an interpolation filter, as well as a timing error detector, a loop filter, and controller that drives the interpolation filter. Generally, the timing error detector estimates residual error in a signal output from the interpolation filter, and the estimated residual error is used by the control loop to adjust a re-sampling time of the interpolation filter. The feedback loop encompassing the interpolation filter, the timing error detector, loop filter, and controller may also be referred to as a phase lock loop (PLL).
Sampling the analog readback signal at the right time instances (or re-sampling/interpolating the digital samples at the right time instances for the case of a digital implementation) is crucial to achieve good system performance. Challenges for STR include speed variations, skew variations, dropout events, and low SNR (signal-to-noise ratio).
A continuing goal in the data storage industry is that of increasing the density of data stored on media. For tape storage systems, that goal has led to increasing the track and linear bit density on recording tape, and decreasing the thickness of the magnetic tape medium. However, increasing the track and bit density on recording tape results in problems, such as decreased SNR.
The conventional approach for STR in tape systems employs independent second order PLLs per read channel, which are optimized for optimum noise rejection and minimum sampling jitter. Tape systems with classical STR schemes fail at low SNR due to high cycle slip rates. A cycle slip may occur when, during the parallel reading of a medium having multiple parallel channels, a timing estimate or timing-error estimate of one or more of the channels is noisy, and the timing erroneously advances by a full bit length, causing a bit of information to be lost. A cycle slip may also occur when, during the parallel reading of a medium having multiple parallel channels, a timing estimate or timing error of one or more of the channels is noisy, and timing retreats by a full bit length, causing a bit to be erroneously inserted.